1. Field of the Invention
This invention relates to a semiconductor memory device for shortening setup time and hold time of command control signals used in synchronous DRAM (Dynamic Random Access Memory) for performing input of addresses and commands, and input and output of data synchronously with external clock signals.
2. Description of the Related Art
In recent years, synchronous DRAM devices have appeared which not only have high speed, but can synchronize with external clocks at frequencies in excess of 100 MHz. These high speed devices require even tighter specifications for setup time and hold time than is needed with conventional devices.
One example of the related art for a command decode method in a synchronous DRAM can be seen in Japanese Patent Laid-open Hei 7-141870. This synchronous DRAM is provided with a clock input terminal CLK, command input terminals CKE, CSB, RASB, CASB, WEB and DQM (Low enable signals are shown here with a B at the end of the signal name.) address input terminals A0-Ai, and data input/output terminals DQ0-DQj. Input of addresses and commands and input/output of data are triggered by the rising edge of the pulse of the external clock signal CLK.
FIG. 6 shows a block diagram of one example of the above-mentioned command decode method. A memory device 200 has an input buffer circuit 1 connected to an external clock signal CLK input terminal 21. This input buffer circuit 1 has a clock enable terminal to control whether or not to output the clock signal that was input. The output terminal is connected to serially connected drive buffers N1 and N2 in that order. The drive buffer N2 outputs the internal clock signal ICLK.
An input buffer circuit 2 is connected to an external clock enable signal CKE input terminal 22. The output terminal is connected to serially connected drive buffers N3 and N4 in that order. An output terminal of the drive buffer N4 outputs an internal clock enable signal ICKE and is connected to the enable terminal of the input buffer 1.
An input buffer circuit 3 is connected to a chip select signal CSB input terminal 23. An input buffer circuit 4 is connected to a row address select signal RASB input terminal 24 and an input buffer 5 is connected to a column address select signal CASB input terminal 25. An input buffer circuit 6 is connected to a write enable signal WEB input terminal 26. These input buffer circuits 3 through 6 are each connected to both of decode circuits 9 and 10 by means of output signal lines A1 through A4.
The output terminal of the command decode circuit 9 is connected to a latch circuit 11 by means of a decode output line C1 and the latch circuit is also fed with an internal clock delay skew signal ICLK1. This latch circuit 11 supplies the mode control signal MODE1 to internal circuits (not shown).
A output terminal of the command decode circuit 10 is connected to a latch circuit 12 by means of a decode output line C2 and the latch circuit is also fed by an internal clock delay skew signal ICLK2. This latch circuit 12 supplies a mode discriminator signal MODE2 to the internal circuits.
The operation of the memory device 200 is explained next. First, the external clock signal CLK is fed into the input buffer circuit 1. This input buffer 1 is fed with the internal clock enable signal ICKE, and is triggered by the internal clock enable signal ICKE outputted from the drive buffer N4. This input buffer circuit 1 is triggered when the internal clock enable signal ICKE is at a high logic level (hereafter called H level). The external clock signal CLK is input and the internal clock signal ICLK is fed to the internal circuits.
In this example, in order to shorten the time needed up to the decode timing and to simplify the circuit, the command control signals; chip select signal CSB, row address strobe signal RASB, column address strobe signal CASB and Write Enable signal WEB are inputted to the input buffers 3-6 and then transferred to the command decode circuits 9 and 10. The command decode signals which are the outputs from the command decode circuits 9 and 10, are latched with the edge of the rise pulse of ICLK1 and ICLK2 into the latch circuits 11 and 12.
The address signals are utilized for final mode discrimination but are omitted from the drawings for the sake of simplicity.
The timing chart for the command decode method is shown in FIG. 7. When the signal CKE is at H level, the external clock signal CLK is valid. The command control signals (CSB, RASB, CASB, WEB) are input so as to contain the setup time (tSE) and hold time (tHE) versus the external clock signal.
The output signals A1 through A4 change after the amount of time (t0) required to pass through input buffer circuits 3 to 6. The signal from the output lines C1 through C2 are delayed by the time caused by the wire length between the input buffer circuits 3-6 and the command decode circuits 9 and 10 and also by the times (t11 and t12) needed to pass through the command decode circuits 9 and 10. These delayed signals are latched with the edge of the rise pulse of the internal clock ICLK into the latch circuits 11 and 12, respectively. Here since the internal clock signal ICLK has skew .DELTA.t resulting from delay due to wire length, the internal clock signals fed into the latch 11 and 12 are listed as the internal clock skew signals ICLK1 and ICLK2.
Another example of a command decode method is shown in the block diagram of FIG. 8. In a memory device 300, the input buffer circuit 1 connected to the external clock signal CLK input terminal 21 has an enable terminal to control whether or not to output the clock signal. The buffer output is connected to the serially connected drive buffers N1 and N2 and to a delay circuit 7. The drive buffer N2 outputs the internal clock signal ICLK and the output of the delay circuit 7 is connected to serially connected buffers N3 and N4.
An input buffer circuit 2 is connected to a clock enable signal CKE input terminal 22. A output of input buffer circuit 2 is connected to serially connected drive buffers N3 and N4. The drive buffer N4 output a internal clock enable signal ICKE.
An input buffer 3 is connected to signal terminal CSB input terminal 23. A output from the input buffer circuit 3 is connected through the output line A1 to the flip-flop D-F/F 8a supplied with the internal clock skew signal ICLK1.
A row address select signal RAS input terminal 24 connects to an input buffer circuit 4. The output from this input buffer circuit 4 connects by means of output line A2 to the flip-flop D-F/F 8b to which is supplied the internal clock signal ICLK2.
A column address select signal CAS input terminal 25 connects to an input buffer circuit 5. The output from the input buffer circuit 5 connects by means of output line A3 to flip-flop D-F/F 8c to which is supplied the internal clock skew signal ICLK3.
A write enable signal WE input terminal 26 connects to an input buffer circuit 6. The output from this input buffer circuit 6 connects by means of output line A4 to flip-flop D-F/F 8a-8d to which is supplied the internal clock skew signal ICLK4. The outputs from these flip-flops D-F/F 8a-8d connect to both of the command decode circuits 9 and 10.
The output from the command decode circuit 9 is connected through a decode line C1 to a latch circuit 11 supplied with an internal clock delay skew signal ICLKD1. This latch circuit 11 supplies the mode control signal MODE1 to the internal circuits.
The output from the command decode circuit 10 is connected through a decode line C2 to a latch circuit 11 supplied with an internal clock delay skew signal ICLKD2. This latch circuit 12 supplies the mode discriminator signal MODE2 to the internal circuits.
In the operation of the semiconductor memory device 300, the external clock signal CLK is input through the input buffer circuit 1. This input buffer 1 is triggered by an internal clock enable signal ICKE in the same manner as given in the example previously related for semiconductor memory device 200. In this example, the command control signals CSB, ETSB, CASB, WEB are supplied through the input buffer circuits 3-6, synchronized with the rising edge of the internal clock signal ICLKi, and loaded and held by flip-flops D-F/F 8a-8d, respectively.
These now loaded signals are supplied to the command decode circuits 9 and 10. The decoded outputs from these command decode circuits 9 and 10 are supplied to the latch circuits 11 and 12 through the output lines C1 and C2, respectively, and latched with the rising edge pulse of internal clock delay signals ICLKD1 and ICLKD2. The latch circuits 11 and 12 which respectively output the mode discriminator signals MODE1 and MODE2. In this way, the latch circuits function to prevent noise and other interference from intruding into the mode discriminator signal.
A timing chart for this command decode method is shown in FIG. 9. When the external clock enable signal CKE is at H level, the external clock signal CLK from the buffer circuit 1 is valid. The input of command signals (CSG, RASB, CASB, WEB) are input so as to retain the setup time (tSE) and hold time (tHE) versus the external clock signal CLK in the same manner as previously related for the semiconductor memory device 200.
Here, the output lines A1-A4 are delayed and changed versus the command signals, by the time (t0) required to pass through the input buffer circuits 3-6. These signals are latched with the rising edge pulse of internal skew clock signals ICLK1 into flip-flops D-F/F 8a-8d, respectively.
The signal from the output lines C1-C2 change after the time caused by the wiring length from each of the flip-flops D-F/F 8a-8d to the command decode circuits 9 and 10, and the time (t11, t12) required to pass through the command circuits 9 and 10.
These changes in the output lines C1-C2 are latched with the rising edge pulse of internal clock delay signal ICLKD from the delay circuit 7, into the latch circuits 11 and 12.
The internal clock delay signal ICKLD has a skew factor just as the internal clock signal ICLK does, so these internal clock delay signals ICKLD are labeled as internal clock delay skew signals ICLKD1 and 2. The delay time provided by the delay circuit 7 is set to wait from the rise pulse of the internal clock signal ICLK by the change time (t21) in the output lines C1-C2, so that the internal clock delay signals ICLKD rise.
The sum (internal window width) of the setup time (tSI) and hold time (tHI) for the chip in the above-mentioned semiconductor memory devices 200 and 300 must be considered. In the case of the timing chart for the semiconductor memory device 200 as shown in FIG. 7 considered for simplicity as,
t11&gt;t12, .DELTA.t (skew of ICLK2 versus ICLK1) and assuming EQU tSE+tHE=tSI+tHI+(t11-t12)+.DELTA.t (1)
then the problem occurs of the internal window width becoming smaller, {by the amount (t11-t12)+.DELTA.t} than the external window width.
Further, when the skew width, .DELTA.t=ICLK in the timing chart for the semiconductor memory device 200 as shown in FIG. 9 then, EQU tSE+tHE=tSI+tHI+.DELTA.t (2)
so that the problem occurs of the internal window width becoming smaller than the external window by an amount equal to the time .DELTA.t. In this case, this reduction of internal window width versus external window width was small enough to be ignored in conventional specifications for setup and hold times. However, with the appearance of high speed DRAM devices in recent years having high speed operation in excess of 100 MHz, the window width becomes narrower and narrower due to the smaller clock period. Consequently in the specifications for the newer high speed devices, the ratio of a reduced window versus the other window becomes a problem that cannot be ignored.